Semiconductor architecture & hardware verification

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Silicon & Microarchitecture

A technical publication covering VLSI design, Verilog/SystemVerilog hardware verification, RISC-V processor architecture, and chip fabrication pipelines.

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● riscv_alu.sv

module riscv_alu (
    input  logic [31:0] a, b,
    input  logic [2:0]  alu_op,
    output logic [31:0] result
);
    always_comb begin
        case (alu_op)
            3'b000: result = a + b; // ADD
            3'b001: result = a - b; // SUB
            default: result = '0;
        endcase
    end
endmodule

Hardware Dispatches

Showing 3 posts

#riscv 7 min read

Designing a Pipelined RISC-V Processor in SystemVerilog

Handling hazard detection, data forwarding paths, and control hazard flushing in 5-stage RISC-V core architectures.

OCT 2026 Read Dispatch

#verilog 8 min read

Modern Hardware Verification with UVM & Universal Testbenches

Building constrained-random stimulus generators, scoreboards, and functional coverage monitors for complex SoC designs.

OCT 2026 Read Dispatch

#vlsi 6 min read

Static Timing Analysis (STA) & Clock Tree Synthesis Basics

Evaluating setup and hold time violations, clock skew, and delay paths in sub-micron semiconductor fabrication nodes.

SEP 2026 Read Dispatch

The Intersection of Silicon & Microarchitecture

Hardware Dispatches

Designing a Pipelined RISC-V Processor in SystemVerilog

Modern Hardware Verification with UVM & Universal Testbenches

Static Timing Analysis (STA) & Clock Tree Synthesis Basics

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The Intersection of
Silicon & Microarchitecture